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Fast Viterbi Decoder IIp - Capable of 1symbol/1clock
decoding
The Viterbi decoder is a forward error correction
(FEC) decoder for covolutional codes used in various communication
systems including INMARSAT, INTELSAT, DVS, and IEEE802.11.
The Viterbi decoder needs a large-scale hardware
for searching a maximum likelihood path. So, it has been difficult
to design high-speed Viterbi decoder with a small-scale hardware.
ML-LABO has invented a new algorithm for accelerating
Viterbi decoder with a small-scale hardware. The Fast Viterbi
Decoder IIp is accelerated by the algorithm, not by being optimized
for Xilinx FPGA architecture. So, the Fast Viterbi Decoder IIp
achieves an excellent performance even if it is implemented
on ASIC.
In addition, the Fast Viterbi Decoder IIp
is capable of 1symbol/1clock decoding unlike Fast Viterbi
Decoder Ip. So, the Fast Viterbi Decoder IIp is easy to use.
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Family List
| Product Code |
R |
k |
Architecture |
Decoding Mode |
| IP-FV7P-CP2 |
1/2
Puncture |
7 |
Parallel (64
ACSs) |
Continuous |
 IP-FV7P-CP2
Data Sheet |
Benchmark
| Product
Code |
Target Device: Xilinx X2V1000-6
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Slices
|
Block
RAMs |
Gates |
Latency |
Clock
Freq.
(Max.) |
Data
Rate
(Max.) |
| IP-FV7P-CP2 |
4,310 |
- |
108K |
92+2 clocks |
91 MHz |
91 Mbps
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Design Kits
| Product Name |
Product Code |
Features |
| Fast Viterbi Decoder Design
Kit |
DK-FV7P-CP2 |
IP-FV7P-CP2 Design Kit |
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Ordering Information
| Product
Name |
Fast Viterbi Decoder
IP Core |
| Product
Code |
IP-FV7x-yP2 x=P,H y=B,C |
| Features |
- Delivery Format: VHDL Source Code
- Constraint Length: k=7
- Code Rate: R = 1/2 Puncture
- Generator Polynomial: Specified at time of order
(Default: G0=171, G1=133)
- Soft Decision: Specified at time of order
(Default: 3bits)
- Capable of 1Symbol/1Clock Decoding
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| Package
Content |
1) One CD-R media that
recorded the VHDL source code files, test bench files, and
user's manual. 2) Licence agreement. 3) User registration
form. |
| License
Condition |
The IP cores can be
implemented on the apparatuses of arbitrary quantity, as
long as the IP core is implemented on the apparatuses of
same design. |
| Product
Name |
Fast Viterbi
Decoder Design Kit |
| Product
Code |
DK-FV7x-yP2,
x=P,H y=B,C |
| Features |
The design kit for IP-FV7x-yP2 IP core.
We recommend the usage of the design kit for the customers
who want to customize the IP core by themselves.
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| Package
Content |
1)
One CD-R media that recorded "tool for verifying design
parameters", "software simulator for analysing BER", "tool
for generating test bench", and user's manual. 2) Licence
agreement. 3) User registration form. |
| Requirements |
Windows
2000, Windows XP, Pentium-compatible CPU. |
| License
Condition |
The license
is valid for one year. While the licence is valid, it can
be used for any design. |
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